This article sets out to demonstrate that for many hobbyist applications, use of a single large value ceramic capacitor is superior to multiple differently-valued capacitors for power supply decoupling.
These pictures are for the modelling of decoupling capacitors on a 2-layer PCB, in TINA-TI simulation software. The conclusions drawn here may not necessarily be applicable for 4-layer boards, where many inductances are halved due to the 10mil (as opposed to 62mil) layer spacing, the power and ground planes have significant built-in capacitive coupling, and the because of the presence of a low inductance power plane which can be used in place of power traces.
The TINA-TI schematic file is available here. Open the file with TINA to run the simulation.
A Simple Example
A basic decoupling circuit consisting of a single SMD capacitor (X5R 0603 10µF) looks like this. A circuit inside an SOT package draws current from a power line. The package itself, as well as the pad and traces, have parasitic RLC components to them. RLC equivalents of some common elements are supplied at the top left for easy copy-pasting into the circuit diagram.
The capacitor here consists of three parts. At the top is a 900pH inductor, corresponding to current flowing a 6 mil distance, 62 mils above a ground plane (return path). This is followed by the RLC model of the capacitor (test results for Murata’s ceramic capacitor catalog are available here). Note that due to voltage derating effects on ceramic capacitors, the true capacitance with a 3.3VDC bias is significantly lower than the specced 10uF. Following this is the RL equivalent of a via to ground. In this particular model I assume that the power trace passes directly through the capacitor pad, and that the trace from the other capacitor pad to the via is negligible. With different fanout lengths it may be necessary to add traces on the capacitor lines as well.
To the right of the capacitor is the trace, in this case 3 inches long at 20mil width, between it and the power supply. For designs with offboard power supplies, it will be necessary to calculate the inductance of the wires involved. The supply here is assumed to be ideal with 0Ω of output impedance.
Running an AC transfer function (CTRL-ALT-A, or Analysis -> AC Analysis -> AC Transfer) from 1kHz to 100GHz produces the graph below.
Note that the Y-axis is labelled “Gain”, as would be expected for an AC transfer function. This graph represents the effect of an input current at IG1 on the voltage at VF1. This is then really the impedance of the decoupling circuit to ground (reference 0V), as measured from the inside of the IC. The Y-axis can be renamed to reflect this. Set the scale from “dB” to “Logarithmic”, and adjust the limits as appropriate. The axis text can now be changed to ohms – the linear relationship between current and voltage.
I have marked here the different regimes where a given component dominates the overall impedance. Inductor impedance rises with frequency while capacitor impedance falls with frequency; regions with a slope of 0 are dominated by resistive effects. Generally, items physically closer to the IC have a greater effect on the high frequency response as there is less parasitic inductance separating them.
The parasitic peaks displayed here are much larger than they would be in reality; I am modelling these as discrete capacitors rather than the distributed capacitance that they actually are. Their values are also incredibly small; characteristics of the IC itself, such as gate capacitance, will often be orders of magnitude larger than these effects. For now I will focus on the lower frequency regime, up to 1GHz (a 1ns rise/fall time).
At low frequencies, the capacitor doesn’t have enough charge to handle prolonged changes in voltage and the resistance to the power supply dominates. The capacitor takes over just as the inductance to the power supply is beginning to appear. On some capacitors, the bottom of their trough may be flattened due to ESR; here, however, its effect is not significant. After that, the inductance of the shortest path to ground (through the decoupling capacitor) becomes the limiting factor.
Conventional wisdom dictates that smaller valued capacitors have lower parasitics. Online guides and message boards generally recommend a ~10µF capacitor with a ~100nF capacitor added in parallel to handle faster signal edges.
Here I use the same 10µF capacitor as before, with an additional 100nF 0402 X7R.
There is now a peak at 7MHz due to anti-resonance (the L and C components of the separate capacitors interact to block these frequencies). This is directly in the middle of the frequencies of interest. However, whether or not this is a big deal is up for debate. A 1Ω peak is not all that significant; a 10mA current draw at that frequency would only result in 10mV voltage droop. That said, the response is not significantly improved over the single larger capacitor.
Though there is a small improvement at high frequencies where signal edges would appear, a similar amount is also lost at typical fundamental signal frequencies. Arguably the 0402 capacitor is still an improvement, as it does manage to eke out a slightly higher bandwidth. But since the majority of a capacitor’s inductance is due to its package size, it would be reasonable to expect an 0402 (as opposed to 0603) 10µF capacitor alone to produce comparable improvements, as is indeed the case.
One Step Further
To take the old rule of thumb to an extreme, we might try pairing an 0603 10µF bulk ceramic capacitor with various different small capacitors in place of the 100nF and see what happens.
As the difference in capacitor values grows, so too do their resonant peaks. The X7R responses are less pronounced than the C0G ones, in part due to their values being closer, but also in part due to their slightly higher ESR values (15mΩ vs 3mΩ) providing damping. Notably, since ESL is almost entirely determined by package size for similarly high-performance capacitor designs, the impedance at very high frequencies is the same for all the capacitor values used.
Changes in Technology
The old rules of thumb come from a time when things like 10µF ceramic capacitors did not exist. In The Art of Electronics, virtually every capacitor 1µF and above is assumed to be a high ESR/ESL tantalum or aluminum electrolytic. The same goes for the datasheets and application notes for many of the older, now classic, ICs. Using, for instance, a single 100µF aluminum electrolytic produces the following (in green):
It is difficult to find reliable ESL measurements of aluminum electrolytic capacitors. I am using the values for ESR given by Rubycon’s low ESR TKV series combined with a 16nH ESL number mentioned in this Analog Devices article.
Although the impedance for a single 100µF electrolytic around 10kHz is marginally lower thanks to the higher capacitance, the ESL takes over quickly at higher frequencies compared to the ceramic capacitor circuits. The capacitor’s high ESR, even compared to the resistance of the power trace, also contributes to the poor performance (this is why older books and documents stress the importance of ESR so much). This setup is still significantly better than no decoupling capacitor at all (blue).
Yet better still is the small ceramic in parallel with the larger electrolytic (purple). So much better, in fact, that one might wonder why – even with the relatively low capacitance of the ceramic – the electrolytic capacitor is necessary at all. The anti-resonance at 2MHz proves too much in this case (grey); the ESR of the aluminum capacitor, combined with its effect of somewhat taming the inductive peak with its own capacitive trough, is necessary to keep the ceramic in check.
Another approach to the problem might be from the other direction. Though the electrolytic capacitor’s reduction of the lower frequency impedance is not useful to us, its role in creating a low pass filter is. This serves to filter out external noise on the power line around the signal’s fundamental frequency.
Given the cost, complexity, and performance advantages of using a single capacitor as opposed to multiple, this approach makes the most sense for decoupling signals around 1MHz on a 2-layer PCB.
Since ESL is primarily package-dependent in this case (dominated by the PCB return path) and ESR for most ceramic capacitors is too low to be relevant, only capacitance affects performance within a single package size. As expected, larger values are generally better.
As for packages it’s more of a toss-up. Any of these would be fine, though the smaller packages do provide better high frequency performance.
Overall, my preferences would tend towards 10µF capacitors in 0603 or 0402 packages, simply because the cost is so negligible. In quantities of 100 they can be found for under a cent apiece. Although 1µF capacitors can be found even cheaper, at that point the assembly fee for soldering the capacitors into place begins to overtake the cost of the capacitors themselves.